http://jcste.ict.ac.cn/paper/hww_071.pdf
Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology
Wei-Wu Hu 1,2, Ji-Ye Zhao 1,2, Shi-Qiang Zhong 1,2, Xu Yang 1,2, ElioGuidetti 3, and Chris Wu 3
1 Key Laboratory of Computer System and Architecture, Chinese Academy ofSciences, Beijing 100080, China
2 Institute of Computing Technology, Chinese Academy of Sciences, Beijing100080, China
3 ST Microelectronics, 39 Chemin du Camp-des-Filles, 1228 Plan Les Ouates,Geneva, Switzerland
E-mail: {hww, jasonzjy, zhongshq, yangxu}@ict.ac.cn; {Elio, Chirs.Wu}@st.com
Received September 27, 2006; revised December 5, 2006.
Abstract
This paper introduces the microarchitecture and physical implementation ofthe Godson-2E processor, which is a four-issue superscalar RISC processorthat supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-basedmethodology with some bit-sliced manual placement and a number of craftedcells and macros. The processor can be run at 1GHz and achieves a SPECCPU2000 rate higher than 500.
Keywords
general-purpose processor, superscalar pipeline, out-of-order execution, non-blocking cache, physical design, synthesis flow, bit-sliced placement,crafted cell, performance evaluation
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